With current state-of-the-art IC processes, the metal lines can only be driven a particular distance before transition time and signal integrity potentially become problematic. For example, in a known IC fabrication process, the metal lines have a width of only approximately 0.28 micrometers (μm). These metal lines can only be driven approximately 1300 μm before the transition time and integrity of the signal become questionable.
When designing latch arrays that are taller than the length that a signal can be driven before transition time and signal integrity become a problem (e.g., >1300 μm), the slow transition times and poor signal integrity resulting from the wire length is a limiting factor with respect to the maximum number of entries that the latch array can have. For example, FIG. 1 illustrates two latches 2 and 3 of a column 1 of a latch array. The outputs of the latches 2 and 3 are tied together. When data is read out of the top latch 2, the data propagates down the column 1 past each of the latches in the column before it reaches the bottom of the latch and is output from memory. Of course, a typical memory element would have a large number (e.g., 256) of columns and a large number of latches (e.g., 128) and a large number of latches per column, although only a single column is shown in FIG. 1.
If the length of the line 4 from the output, DOUT, of latch 2 to the bottom end 5 of the column 1 is greater than the length limit mentioned above, the signal output from the latch 2 will likely have poor integrity and/or a transition time problem. Transition time problems can lead to problems such as, for example, setup time violations. Of course, signal integrity problems can lead to improper states being detected by the downstream logic, as can transition time problems. The common solution for preventing such problems is to interrupt the line 4 output from the upper latch with a buffer, or repeater, that will ensure that the output signal is driven with sufficient strength to prevent transition time and/or signal integrity problems. The configuration for this approach is shown in FIG. 2
In accordance with the configuration shown in FIG. 2, if the upper latch 8 is addressed by asserting the Enable signal of the upper latch 8, the output, DOUT, of the upper latch will be received by the buffer 9, which will further drive the output signal so that no transition time or signal integrity problems occur. However, a multiplexer 7 is needed for the pair of latches in order to convert the two signal lines 10 and 11 into a single signal line 12. If the upper latch 8 is addressed by asserting its Enable signal, then the select line will select the signal on line 10. If the lower latch 13 is addressed by asserting its Enable signal, then the select line will select the signal on line 11.
Although the approach shown in FIG. 2 operates to prevent transition time and/or signal integrity problems from occurring when data is output at the bottom of the column 15, there are several disadvantages associated with this approach. One disadvantage is that the multiplexers required to implement this approach increase the costs and complexity of the latch array and consume a considerable amount of area on the IC. Also, typically multiplexers are much slower than buffers, and thus there is a performance penalty associated with the multiplexer approach. Another disadvantage of this approach is that the two lines 10 and 11 double the number of lines that the latch array would have if a configuration such as that shown in FIG. 1 were implemented. This also increases costs and routing complexity, as well as the amount of area on the IC required for implementation of the latch array.
Accordingly, a need exists for a latch array that ensures that transition time problems and signal integrity problems will not occur, and which minimizes the amount of area required to implement the latch array and the routing complexity of the latch array, which enables the costs associated with implementing the latch array to be minimized.